1) Field of the Invention
The present invention relates to a technology for timing analysis of a digital circuit, and more particularly to a technology for detecting a timing exception path.
2) Description of the Related Art
Timing analysis is an essential process in manufacturing a digital circuit for ensuring a proper operation of the digital circuit. In the timing analysis, a delay is estimated from a design of the digital circuit, and it is determined whether the delay is within a range that allows the digital circuit to operate normally. For the timing analysis, not only a netlist of the digital circuit to be designed, but also timing restriction information is necessary. The timing restriction information includes specifications for a clock, a mode, delay restriction, and a timing exception path, such as a multi-cycle path and a false path.
The netlist can be created, to some extent, automatically with a computer aided design system (CAD) tools such as logical synthesis tools and layout tools, the netlist of the digital circuit being designed can, to a certain extent. On the other hand, the timing restriction information is usually created manually. Since the amount information in the timing restriction information has not been very large, the timing restriction information has been manually generated without problems hitherto. However, recently, the timing restriction information is becoming more complex, and a speed and a scale of the digital circuit is increasing. As a result, it is becoming difficult to manufacture a digital circuit that operates according to a given clock cycle.
Accordingly, there is an increasing demand for a technology for efficiently detecting as many timing exception paths as possible. The timing exception paths include a path of which a delay of a path between arbitrary two sequential circuit elements in the digital circuit is not necessary to be confined to a single clock cycle, such as a multi-cycle path of which the delay may acceptably be two or more clock cycles, and a false path whose delay does not affect the delay of the entire circuit.
In a conventional technology for detecting such timing exception paths from a digital circuit, it is detected whether a path is a timing exception path for each of paths between sequential circuit elements. In another conventional technology, paths between sequential circuit elements are handled in a set, and such detection is performed for each of a combination of the sequential circuit elements in a unit of the combination. Such technologies are disclosed in, for example, Japanese Patent Application Laid-open Nos. 2003-157297 and 2004-171149.
In the conventional technology, in worst cases, an exponential explosion occurs on the path with respect to a circuit scale. Therefore, a calculation time for the detection greatly increases. In addition, when an amount of information on the timing exception path is large, calculation time of timing analysis tools that receive such information also increases.
On the other hand, in another one of the conventional technologies, it is possible to avoid such problems caused by increased number of paths. However, for example, when only some of the paths between arbitrary two sequential circuit elements are the timing exception paths, these timing exception paths cannot be detected.
The timing exception path includes the multi-cycle path and the false path, and analysis for the timing exception path is performed independently for each of the multi-cycle path and the false path. Such analysis is often redundant in terms of the analysis for the timing exception path as a whole, and this also leads to increase of the calculation time.
Recently, for manufacturing digital circuits, there is a demand to efficiently detect the timing exception paths during the circuit design stage with high accuracy, and to shorten a manufacturing period of digital circuits with increasingly complexity.